Release Notes & Changelog

Track every architectural milestone, hardware optimization, security hardening tier, and protocol integration across the Eluvix Sovereign AI Routing Gateway (@eluvix/router-core, apps/nextjs, apps/desktop, and @eluvix/opencode-harness).

v1.0.14 — Rail-Optimized 400G/800G Clos Fabrics & Unified Multi-Harness Studio (October 29, 2026)

🕸️ Rail-Optimized Leaf-Spine Clos, BGP EVPN, SRv6 uSID & Switch DLB (@eluvix/router-core)

• Balls-into-Bins ECMP Hash Polarization Combinatorics (calculateEcmpHashPolarization):
  • Exact combinatorial modeling of static 5-tuple ECMP hash collisions when M synchronized 400Gbps/800Gbps RoCEv2 Queue Pairs ("elephant flows") traverse K Leaf-to-Spine uplinks: P(zero collision) = K! / (K^M * (K - M)!) ≈ 0.24% (99.76% collision probability for K = 8, M = 8) and E[Idle Uplinks] = (1 - 1/K)^M ≈ 34.36% (~2.75 idle links), explaining why standard ToR ECMP collapses to 41.0% effective AllReduce bus bandwidth (derived from exact Multinomial DP distribution of maximum bin load; empirical cluster measurements ~44.6%) and triggers Priority Flow Control (PFC) pause storms.
• 8-Rail Plane-Separated Clos + NCCL PxN (NCCL_PXN_DISABLE=0):
  • Models Rail-Optimized wiring where NIC i of every 8-GPU node connects to Rail i Leaf Switch, enabling single-hop ~380ns cut-through intra-rail AllReduce and intra-node 900 GB/s NVSwitch proxying (NCCL_CROSS_NIC=1, NCCL_IB_QPS_PER_CONNECTION=4) to reach 84.8%+ effective bus utilization.
• 128-Bit SRv6 Micro-SID (uSID, RFC 8986) Carrier & 8ns Hardware Bit-Shift (encodeAndSimulateSrv6Usid):
  • Encodes explicit source-routed Spine and Egress Leaf paths directly inside the 128-bit IPv6 Destination Address (fcbb:bb00:0202:0104:0040::) with 0 bytes of SRH extension header overhead (saving 56 bytes per packet vs legacy 3-SID SRH).
  • Simulates the 8-nanosecond End.uN 16-bit left shift at the Spine ASIC (fcbb:bb00:0104:0040::) and End.uDT4 VRF decapsulation at the Egress Leaf (fcbb:bb00:0040::), plus collision-free disjoint Spine scheduling (planDeterministicSrv6SpineSchedule).
• Switch Dynamic Load Balancing (DLB) & ConnectX-7/8 Out-of-Order Direct Data Placement (OOO-DDP):
  • Added simulateOooDdpBitmapWindow modeling ConnectX-7/8 SuperNIC hardware PSN sliding bitmap tracking (OO_RECV_WR_EN=1, ROCE_ADAPTIVE_ROUTING_EN=1) that DMA-writes out-of-order sprayed packets directly to their exact GPU HBM3e byte offset (base + (PSN - basePsn) * 4096) with zero Go-Back-N retransmissions, achieving 452 GB/s MoE AllToAll bus bandwidth (2.69x speedup, 97.8% line-rate utilization).
• Fabric-Aware Switchyard Policy (fabricPolicy) & Config Generators:
  • Added fabricPolicy: 'disabled' | 'prefer-rail-optimized' | 'require-collision-free-fabric' to Switchyard, x-eluvix-fabric-topology / x-eluvix-rdma-transport / x-eluvix-srv6-usid-carrier response headers, SONiC FRRouting RFC 8950 BGP Unnumbered frr.conf + Linux host script generators, Interactive Clos Fabric Lab on /provider, and Bundled Example 18 (rail-optimized-srv6-dlb-moe-fabric).

🤖 Multi-Harness Adapters & Unified Agent Harness Studio (/harness)

• Expanded first-class harness protocol adapters to 8 runtimes: TrueForge (:8790), OpenHands (:3000), Mastra (:4111), Letta / MemGPT (:8283), A2A (Agent2Agent JSON-RPC 2.0) (:8900), opencode (:4096), ACP (stdio JSON-RPC 2.0), and Hermes (:8642).
• Added the Unified Agent Harness Workbench Modal & /harness Studio with live turn streaming, tool approval interception, and session state inspection.

v1.0.13 / v1.0.12 / v1.0.11 — In-Process TrueForge & Eluvix-Forked OpenCode (@eluvix/opencode-harness) (October 28, 2026)

🛠️ Deep Agent Loop Integration (@eluvix/opencode-harness & In-Process TrueForge)

• Eluvix-Forked OpenCode (packages/opencode-eluvix):
  • Intercepts every intermediate agent turn inside the coding loop before tool outputs re-enter the LLM context window.
  • Mid-Loop DLP & PromptGuard: Automatically scrubs credentials/PII from bash and file-read tool outputs and scans scraped content for indirect prompt injections before the next model turn.
  • Dynamic Step Tiering: Routes initial architectural planning steps to frontier reasoning models, routine file/grep tool steps to $0 local coding models, and final patch synthesis to high-capability coders.
  • KV-Cache Prefix Pinning: Pins the session's SHA-256 system/tool prefix across all turns in an agent trajectory so vLLM and SGLang workers retain warm RadixAttention / PagedAttention KV blocks.
• In-Process TrueForge Engine:
  • Embedded a zero-container, in-process TrueForge execution loop directly inside @eluvix/router-core with full tool registry, read-only auto-approval, and SSE step streaming when no external TrueForge container is running.
• Modular Docker Compose Profiles (docker/compose/):
  • Split monolithic container definitions into composable stack slices: core.yml, inference.yml, harnesses.yml, and memory.yml.

v1.0.10 — Sub-4-Bit Microscaling (NVFP4, MXFP4) & Walsh-Hadamard Outlier Rotation (October 28, 2026)

🧮 Blackwell NVFP4, OCP MXFP4 & Fast Walsh-Hadamard Transform (@eluvix/router-core)

• Two-Level Microscaling Engine (microscaling-quantization.ts):
  • Exact E2M1 (1 sign, 2 exponent, 1 mantissa, bias b = 1, values {0, 0.5, 1.0, 1.5, 2.0, 3.0, 4.0, 6.0}) quantizer comparing standard OCP MXFP4 (32-element block, E8M0 power-of-2 scale, 4.25 bits/weight) against NVIDIA Blackwell NVFP4 (16-element block, fractional FP8 E4M3 Level-1 scale + per-tensor FP32 Level-2 scale, 4.50 bits/weight, PTX tcgen05.mma.kind::mxf4nvf4).
  • Demonstrates why NVFP4 eliminates the E8M0 power-of-2 sawtooth rounding cliff and reduces block quantization MSE by ~2.4x.
• Orthogonal Walsh-Hadamard Outlier Rotation (R1..R4) & SVDQuant:
  • Implemented in-place O(d log2 d) Fast Walsh-Hadamard Transform (fastWalshHadamardTransform) modeling QuaRot / SpinQuant rotations (R1 offline residual stream, R2 per-head H_128 W_V/W_O, R3 online post-RoPE Q/K 4-bit KV rotation, and R4 online fused SiLU_and_Mul epilogue before down_proj) plus SVDQuant rank-32 LoRA outlier absorption.
  • Compresses 100x emergent activation spikes by sqrt(d) (≈ 90.5x at d = 8192), recovering 99.6% of BF16 MATH-500 reasoning accuracy at 3.42x throughput while fitting Llama-3.3-70B on a single GPU (39.4 GB, TP=1).
• Quantization-Aware Switchyard Policy (quantizationPolicy):
  • Added quantizationPolicy: 'disabled' | 'prefer-nvfp4-hadamard' | 'lossless-reasoning', blocking naive weight-only INT4-AWQ/GPTQ or unrotated MXFP4 workers on complex math/coding prompts, emitting x-eluvix-quantization-format, x-eluvix-outlier-rotation, and x-eluvix-tensor-core-ptx headers, plus Interactive NVFP4 Lab on /provider and Bundled Example 17 (nvfp4-hadamard-lossless-reasoning).

v1.0.9 — 22-Finding Security, Routing, Telemetry & Visual Editor Audit (October 27, 2026)

🛡️ Monorepo Bug Hunt & Correctness Hardening

• Security & Locality: Fixed acp:// stdio harness classification under egressPolicy: 'local-only' so undeclared harnesses fail closed unless providerIsLocal: true is explicitly set.
• Dry-Run Route Explanation Parity: Fixed /api/v1/route-explain to forward x-eluvix-confidential, x-eluvix-pd-role, and x-eluvix-effort headers without mutating roundRobinIndex state during dry-run explanations.
• Consensus & Fallback Resiliency: Added automatic memory write-back to executeConsensusGroup streaming responses, immediate fallback chain advancement on upstream HTTP 429 rate limits, and deep structural comparison in diffRouterConfigs.
• Orchestrator & SQLite Telemetry: Added full container deployment support for vllmNode and sglangNode in the local orchestrator and optimized SQLite observability aggregations to single-pass queries.

v1.0.8 — Zero-Trust Confidential Computing (AMD SEV-SNP, Intel TDX & NVIDIA H100/B200 CC) (October 26, 2026)

🔐 Hardware-Rooted CPU & GPU Trusted Execution Environments (confidential-computing.ts)

• Silicon Threat Mitigations:
  • Models and verifies AMD SEV-SNP Reverse Map Table (RMP) + PVALIDATE + Restricted Injection (#HV, vector 28), Intel TDX Secure EPT (S-EPT) + SEPT_VE_DISABLE, and NVIDIA GSP hardware BAR0/BAR1 MMU firewalling (0xFFFFFFFF host readback protection) with SPDM 1.2 AES-GCM-256 DMA encryption.
• Hopper H100 (SWIOTLB Bounce Buffers) vs. Blackwell B200 (TEE-I/O Inline PCIe Gen6 IDE):
  • Quantifies DMA encryption overhead across architectures: Hopper H100 CC-On (8.64 GB/s effective H2D bandwidth, 8.1s cold load for 70GB weights, -5.5% single-GPU decode overhead, 81.4% 8-GPU AllReduce efficiency) vs. Blackwell B200 TEE-I/O (24.20 GB/s H2D via PCIe Gen6 IDE/TDISP, 2.9s cold load, -1.1% decode overhead, 98.6% 8-GPU AllReduce over inline-encrypted NVLink 5).
• IETF RATS Dual-Attestation Verifier & Encrypted tmpfs Weight Unsealing:
  • Verifies combined CPU quote (SHA512(nonce || ephemeral_pubkey) at VMPL 0, DEBUG=0, SMT=0, MIGRATE_MA=0) and ECDSA P-384 signed GPU SPDM 1.2 evidence before releasing the 256-bit AES-GCM Model Weight Decryption Key (DEK) from Trustee KBS (kbs://) into an encrypted RAM-backed tmpfs mount (/mnt/enclave-weights).
• Confidential Switchyard Policy (confidentialPolicy):
  • Added prefer-tee, require-tee, and require-dual-attestation policies with fail-closed HTTP 503 (confidential_enclave_unavailable), x-eluvix-tee-posture / x-eluvix-tee-arch / x-eluvix-rats-kbs headers, Interactive Confidential Silicon Lab on /provider, and Bundled Example 16 (zero-trust-confidential-tee-enclave).

v1.0.7 — Disaggregated LLM Serving & GPUDirect RDMA Fabrics (October 25, 2026)

🌐 Prefill/Decode Disaggregation (vLLM NIXL & SGLang Mooncake)

• Roofline Operational Intensity & KV-Cache Footprint Engine (disaggregated-serving.ts):
  • Models the H100 SXM5 / B200 Roofline ridge point (295.3 FLOPs/Byte on H100), isolating compute-bound Prefill (>2,048 FLOPs/Byte) from memory-bandwidth-bound Decode (16–32 FLOPs/Byte).
  • Exact per-token KV-cache footprint calculator comparing standard GQA-8 (160 KiB/tok FP8 on Llama-3.3-70B) against DeepSeek Multi-Head Latent Attention (MLA) (34.3 KiB/tok FP8 — a 4.66x compression that slashes 4K-token KV transfer over 400GbE RoCEv2 from 12.5 ms to 2.68 ms).
• Layer-Wise Pipelined RDMA Transfer & Switchyard Prefill-Isolation:
  • Simulates overlapping layer-by-layer GPUDirect RDMA PUT transfers with transformer forward computation (96%–98% overlap ratio) using vLLM NixlConnector and SGLang Mooncake.
  • Added Switchyard prefillIsolationThresholdTokens routing, SHA-256 kvPrefixAffinity warm-cache routing, separated x-eluvix-ttft-ms (Prefill) and x-eluvix-itl-ms (Decode) SSE telemetry headers, Goodput SLA tracking, Interactive Disaggregated Serving Lab on /provider, and Bundled Example 15 (disaggregated-pd-rdma-cluster).

v1.0.6 & v1.0.5 — Next-Gen Orchestration Nodes & Tier 1–5 Security Hardening (October 23–24, 2026)

🧩 5 New Visual Routing Nodes & Expanded Ecosystem

• New Canvas Nodes: Added Knowledge Base RAG (knowledgeBaseNode), Semantic Cache (semanticCacheNode), Execution Sandbox (sandboxNode), Consensus / Judge (consensusNode), and Fallback Chain (fallbackChainNode) to the Visual Editor and orchestration compiler.
• Expanded Memory & Graph Backends: Added Graphiti (bi-temporal knowledge graph), LightRAG (dual-level entity/relation + vector RAG), Cognee (ECL graph pipeline), and Supermemory alongside OpenViking, Mem0, and SQLite FTS5.
• Tier 1–5 Security Hardening:
  • Tier 1 (Desktop Server Lockdown): Per-boot random bearer token, strict Origin/Host header verification, and explicit ELUVIX_ALLOW_CLI_EXECUTION gate for CLI subprocesses.
  • Tier 2 (Harness & Memory Safety): Subprocess process.env secret scrubbing at spawn, random-nonce <eluvix-memory> delimiter tags with PromptGuard scanning on recalled memories, and [DONE]-gated stream-tee memory commits.
  • Tier 3 (Identity & Cache Isolation): Proven-identity cache partitioning (v2:{userId}:{routingDigest}:...) and per-user SQLite chat_history scoping.
  • Tier 4 & 5 (Provider Honesty & Ops): Eliminated synthetic fallback models/heartbeats in the GPU Provider daemon, added honest guard dependency warnings, and hardened k3d/Helm/Docker production deployments.

v1.0.4 – v1.0.1 — Sovereign Gateway Foundation, Agent Harnesses & Context Memory (October 13–21, 2026)

• v1.0.4: Integrated Agent Harnesses (TrueForge, opencode, ACP, Hermes) with x-eluvix-hops Loop Guard, Context Memory Engine (OpenViking, Mem0, SQLite) with Cloud Egress Guard (filter / strip), AMD ROCm Docker Compose profiles, and dual-protocol same-port HTTP→HTTPS auto-upgrade on port 3588.
• v1.0.3 & v1.0.2: Added /api/v1/route-explain decision tracing, Switchyard failoverBudgetMs ceiling, automatic vision capability inference for multimodal payloads, interactive config-diff confirmation modal before applying canvas changes, and SSRF private-IP blocklists.
• v1.0.1: Initial public release of @eluvix/router-core, Next.js Visual Node Studio (/editor), Trace Playground (/playground), GPU Provider Portal (/provider), Observability Dashboard (/observability), Multi-Tier Orchestrator (Local, Docker, k3d, Helm), and Electron Desktop App.